mos/dev/include/avr-spi.h

00001 //  This file is part of MOS, the MANTIS Operating System
00002 //  See http://mantis.cs.colorado.edu/
00003 //
00004 //  Copyright (c) 2002 - 2007 University of Colorado, Boulder
00005 //
00006 //   All rights reserved.
00007 //
00008 //   Redistribution and use in source and binary forms, with or without
00009 //   modification, are permitted provided that the following conditions are
00010 //   met:
00011 //
00012 //       * Redistributions of source code must retain the above copyright
00013 //         notice, this list of conditions and the following disclaimer.
00014 //       * Redistributions in binary form must reproduce the above
00015 //         copyright notice, this list of conditions and the following
00016 //         disclaimer in the documentation and/or other materials provided
00017 //         with the distribution. 
00018 //       * Neither the name of the MANTIS Project nor the names of its
00019 //         contributors may be used to endorse or promote products derived
00020 //         from this software without specific prior written permission.
00021 //
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00034 
00035 /* File: avr-spi.h
00036  * Author: john ledbetter (john.ledbetter@colorado.edu)
00037  * Desc: Seperating out AVR specific code from spi.h 
00038  * Date: 5/24/2007
00039  */
00040 
00041 #ifndef __AVR_SPI_H__
00042 #define __AVR_SPI_H__
00043 
00044 
00045 
00046 #define CC2420_CHIP_SELECT_PORT B
00047 #define CC2420_CHIP_SELECT_PIN 0
00048 #define CC2420_CHIP_SELECT CC2420_CHIP_SELECT_PORT, CC2420_CHIP_SELECT_PIN
00049 
00050 #define SPI_CLOCK_PORT B
00051 #define SPI_CLOCK_PIN 1
00052 #define SPI_CLOCK SPI_CLOCK_PORT,       SPI_CLOCK_PIN
00053 
00054 #define SPI_MOSI_PORT B
00055 #define SPI_MOSI_PIN 2
00056 #define SPI_MOSI SPI_MOSI_PORT, SPI_MOSI_PIN
00057 
00058 #define SPI_MISO_PORT B
00059 #define SPI_MISO_PIN 3
00060 #define SPI_MISO SPI_MISO_PORT, SPI_MISO_PIN
00061 
00062 /* extern int spi_int_state; */
00063 
00064 
00065 #define SPI_DISABLE_RX_INT() SPCR &= ~(1 << SPIE)
00066 #define SPI_ENABLE_RX_INT()  spi_int_state = SPI_INT_RECV; SPCR |= (1 << SPIE)
00067 #define SPI_DISABLE_TX_INT() SPCR &= ~(1 << SPIE)
00068 #define SPI_ENABLE_TX_INT()  spi_int_state = SPI_INT_SEND; SPCR |= (1 << SPIE)
00069 
00070 #define SPI_DISABLE_INT() SPI_DISABLE_RX_INT()
00071 
00072 #define SPI_INT_SEND 0
00073 #define SPI_INT_RECV 1
00074 
00075 // other
00076 #define SPI_WAIT() { while (!(SPSR & (1 << SPIF))); }
00077 #define SPI_WAIT_EOTX() SPI_WAIT()
00078 #define SPI_WAIT_EORX() SPI_WAIT()
00079 
00080 #define SPI_TX_BUF SPDR
00081 #define SPI_RX_BUF SPDR
00082 
00083 
00084 #define PLAT_SPI_INIT() do {                    \
00085       init_spi_mutex_stuff();                   \
00086       MASK_2(SPCR, SPE, MSTR);                  \
00087       MASK_1(SPSR, SPI2X);                      \
00088    } while(0)
00089 
00090 
00091 #endif

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