00001 // This file is part of MOS, the MANTIS Operating System 00002 // See http://mantis.cs.colorado.edu/ 00003 // 00004 // Copyright (c) 2002 - 2007 University of Colorado, Boulder 00005 // 00006 // All rights reserved. 00007 // 00008 // Redistribution and use in source and binary forms, with or without 00009 // modification, are permitted provided that the following conditions are 00010 // met: 00011 // 00012 // * Redistributions of source code must retain the above copyright 00013 // notice, this list of conditions and the following disclaimer. 00014 // * Redistributions in binary form must reproduce the above 00015 // copyright notice, this list of conditions and the following 00016 // disclaimer in the documentation and/or other materials provided 00017 // with the distribution. 00018 // * Neither the name of the MANTIS Project nor the names of its 00019 // contributors may be used to endorse or promote products derived 00020 // from this software without specific prior written permission. 00021 // 00022 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00023 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00024 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 00025 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 00026 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00027 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00028 // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00029 // LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00030 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00031 // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 00032 // ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00033 // POSSIBILITY OF SUCH DAMAGE. 00034 #ifdef PLATFORM_TELOSB 00035 00036 #define CC2420_RESET_PORT 4 00037 #define CC2420_RESET_PIN 6 00038 #define CC2420_RESET CC2420_RESET_PORT, CC2420_RESET_PIN 00039 00040 #define CC2420_VREG_PORT 4 00041 #define CC2420_VREG_PIN 5 00042 #define CC2420_VREG CC2420_VREG_PORT, CC2420_VREG_PIN 00043 00044 #define CC2420_FIFO_PORT 1 00045 #define CC2420_FIFO_PIN 3 00046 #define CC2420_FIFO CC2420_FIFO_PORT, CC2420_FIFO_PIN 00047 00048 #define CC2420_SFD_PORT 4 00049 #define CC2420_SFD_PIN 1 00050 #define CC2420_SFD CC2420_SFD_PORT, CC2420_SFD_PIN 00051 00052 #define CC2420_CCA_PORT 1 00053 #define CC2420_CCA_PIN 4 00054 #define CC2420_CCA CC2420_CCA_PORT, CC2420_CCA_PIN 00055 00056 #define CC2420_FIFOP_PORT 1 00057 #define CC2420_FIFOP_PIN 0 00058 #define CC2420_FIFOP CC2420_FIFOP_PORT, CC2420_FIFOP_PIN 00059 00060 // little hack 00061 #define EIMSK P1IE 00062 00063 #define CC2420_FIFOP_INTERRUPT() interrupt (PORT1_VECTOR) fifop_int() 00064 00065 // enable Port 1, Pin 0 (FIFOP) Interrupt 00066 #define PLAT_ENABLE_FIFOP_INT() do { \ 00067 /* P1DIR |= (1 << 0); */ \ 00068 P1IES &= ~(1 << 0); \ 00069 P1IE |= (1 << 0); \ 00070 } while(0) 00071 00072 00073 #endif 00074
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